The present invention relates to integrated circuits and to methods for manufacturing them.
In a new class of integrated circuit fabrication processes taught by the grandparent application (Ser. No. 729,318, filed 05/01/85, pending (TI-11029)), a very novel local interconnect technology was set forth, which resulted in very conveniently produced titanium nitride local interconnect line. These lines can be routed to interconnect p+ substrate regions, n+ substrate regions, and polysilicon in any pattern desired, while also permitting self-aligned silicidation to occur to clad surfaces of exposed silicon substrate areas and also of exposed polysilicon lines with silicide, to improve their conductivity.
In most conventional processes for making floating-gate nonvolatile memories (EPROMs or EEPROMs), the floating-gate memory cells are formed using two separate polysilicon layer. The first layer is typically used only for the floating gates of the memory cells. The second layer is typically used for the control gates of the floating gate memory cells, and also for the gates of MOS devices (i.e. insulated gate field effect transistors) in the periphery. Sometimes the second layer will be silicided to improve conductivity.
In conventional processes for making dynamic random-access memories (DRAMs), the memory cells are formed using two separate polysilicon layer. The first layer is typically used for the gate of the pass transistor, and the second layer is typically used for the top plate of the storage capacitor.
Since thin film deposition steps and patterned etching steps are both significantly expensive process steps. it would be highly desirable to be able to fabricate such devices with a reduced number of polysilicon deposition and etching steps. This would provide reduced fabrication cost, which is most especially important in such "commodity" parts.